Study of the Metal Filling Impact on Standard Cells and their Associated Interconnects Using Ring Oscillators: Definition of the Metal Fill Corner Concept

In advanced very-large-scale integration (VLSI) circuits, the planarity of each metal layer and interlayer dielectric (ILD) is essential to avoid significant yield losses. The primary technique used to attain high levels of planarity is chemical-mechanical polishing (CMP). Several studies of CMP process impact on electrical parameters [1] and planarity [2] are available. In order to reduce the pattern-dependant variation of thickness in the CMP process, each metal layer must have a density included in a range fixed by the technology process. This can be achieved by inserting metal fills in the space between metal shapes of the same layer. However, addition of dummy fill increases the coupling and total interconnect capacitance, leading to timing performance degradation. Multiple efficient interconnect capacitance extraction using floating dummy fill methods have been proposed to quantify this impact. An efficient algorithm based on boundary element method for three-dimensional capacitance extraction is proposed by [3], while [4] studies dummy fills impact on delay, capacitance and crosstalk noise using electrical field. Results about modeling the floating condition of dummy fills using a design of experiment methodology are presented in [5]. Moreover, dealing with the coupling capacitance due to metal filling is a complex problem, especially because several ways of filling can be found in the industry. While [6] demonstrates metal filling impact on circuit performing a full-chip RC extraction, reference [7] studies the capacitance deviation due to both dummy fills and modifications of interconnect geometry. Filling guidelines for one metal layer are exposed in [8] in order both to increase metal density and to reduce dummy fills impact. Trying to manage the balance between high metal density and small coupling capacitance is a real challenge. Filling methods are presented in [9] to both reduce interconnect capacitance and number of dummy fills. Reference [10] presents a methodology to select an optimal metal-fill patterning, taking into account ILD thickness variation and coupling capacitance. However, there are no existing results on statistical study of metal fill patterning variations impact on delay in order to allow designers to predict filling impact on the timing of their cell. In this context, the objective of the paper is to evaluate the delay impact of staggered metal filling on the standard cells and their associated local interconnect considering several metal levels. A DOE approach is used to develop an analytic model. Its ABSTRACT1